As indicated above, this application relates to U.S. Ser. No. 09/595,143, filed Jun. 17, 2000, entitled "Architecture for High Speed Memory Circuit Having a Relatively Large Number of Internal Data Lines", Attorney Docket No. UM-137, naming Kim Carver Hardee and John Heightley as inventors. The full disclosure of that application (U.S. Serial No. 09/595,143) is hereby incorporated herein by reference.
Throughout this specification, reference will often be made to inputs, outputs, lines and busses, among other things, that are included within the preferred form of the memory circuit. Throughout this specification, if reference is made to one of these, such as a data line, and that data line is given a particular reference numeral for identification purposes, then another data line given the same reference numeral but with a "B" designation shall be understood to be its complement. For instance, a data line 300B would be understood to be the complement of data line 300. Conversely, data line 300 would be the complement of data line 300B. Generally speaking, if they are not tied together (such as when they are equalized), or if they are not driven to the same logic state for a special purpose, when data line 300 is HIGH, data line 300B is LOW. Conversely, absent special conditions, when data line 300 is LOW, data line 300B is HIGH. Those skilled in the art will appreciate this concept and understand this designation hereby incorporated herein by reference.
U.S. Ser. No. 09/595,143, filed Jun. 17, 2000 and incorporated herein by reference, is directed to a high speed memory integrated circuit having a relatively large number of data lines. A noted deficiency of memory circuits having a relatively large number of data lines is that during a write operation in which data is stored in memory cells, there typically exists a timing skew between the data lines used for writing the data and the column select line used to select a column of memory cells in which to write the data represented by the signals carried by the data lines. This timing skew limits the performance of the memory circuit.
FIG. 1 illustrates a timing diagram showing a conventional timing scheme for writing data to the storage locations included in a memory circuit. As illustrated, the signal (YW) present on the write column select line is responsive to the same edge of a clock signal (CLK) as the signal present on the write data lines, here the signal (DW) present on a global write data line and its complement signal (DWB) present on another global write data line. In the illustrated case, the column select signal YW and the write data signals DW/DWB are responsive to the positive edge of the clock signal CLK.
The problem with this timing scheme is that in the preferred memory integrated circuit disclosed in U.S. Ser. No. 09/595,143, the write column select signals (YW) are generated below the sense amp bands and the write column select lines extend longitudinally through the sense amp bands, which also extend longitudinally. On the other hand, the write data signals (DW/DWE) are driven by global write data lines that extend laterally across the memory array. Under such circumstances, a timing skew results between the YW and DW/DWB signals, which limits performance of the memory circuit because, as will be appreciated by those skilled in the art, the actual time in which the write operation can be carried out is during the overlap in which the write column select signal YW and write data lines DW/DWB are active (i.e., valid).
It is an object of the present invention to enhance the performance of a memory circuit.
It is another object of the present invention to relax the timing sensitivity of a memory circuit.
It is still another object of the present invention to reduce the timing skew when writing to a memory circuit.
It is yet another object of the invention to clock the data lines and the column select lines on opposite edges of the clock signal.
It is moreover an object of the present invention to develop a reduced timing skew write cycle scheme that increases the ability to design high speed memory circuits having a relatively large number of internal data lines.
These and other objects of the preferred form of the invention will become apparent from the following description. It will be understood, however, that an apparatus and/or method could still appropriate the invention claimed herein without accomplishing each and every one of these objects, including those gleaned from the following description. The appended claims, not the objects, define the subject matter of this invention. Any and all objects are derived from the preferred form of the invention, not necessarily the invention in general.